IPCEI Microelectronics: Building Europe’s Semiconductor Sovereignty
The Important Projects of Common European Interest for Microelectronics — executed in two waves separated by five years — are the foundational instruments of European semiconductor sovereignty. For France, these programs underpin the €7.5 billion Crolles investment and protect Soitec’s global monopoly on FD-SOI wafers: together the most defensible position any EU country holds in advanced chip manufacturing. Total French public support across both IPCEI rounds exceeds €1.8 billion, with a further €1.5 billion from the EU Chips Act.
The Strategic Problem: Europe’s Chip Dependency
In 2018, Europe produced approximately 10% of global semiconductor output — down from 44% in 1990. Three structural shifts drove this decline:
The fabless revolution: US companies (AMD, Nvidia, Apple, Qualcomm) shifted to designing chips while outsourcing fabrication to TSMC and Samsung. European chip designers either followed suit or were marginalized.
Leading-edge concentration: Advanced process nodes (below 10nm) consolidated to TSMC (Taiwan) and Samsung (South Korea). European fabs specialized in mature nodes — profitable but strategically dependent.
Underinvestment cycle: Without leading-edge fabs, Europe attracted fewer chip designers, which reduced demand for European fabs, which justified less investment — a self-reinforcing decline.
The EU’s stated target: reach 20% of global semiconductor output by 2030. France 2030 and IPCEI Microelectronics are the primary instruments for achieving France’s share of that target.
IPCEI ME I: December 2018 — The Inaugural IPCEI
IPCEI Microelectronics I was approved December 18, 2018 — predating France 2030 by three years, but fully absorbed into France 2030’s funding architecture when the plan launched in October 2021.
Structure:
- 8 EU member states
- €1.75 billion total public funding
- €6 billion private investment catalyzed
- 29 direct project participants
- Focus: compound semiconductors (GaN, SiC), silicon photonics, advanced packaging, and next-generation transistor architectures
The program’s technology focus — wide-bandgap semiconductors and FD-SOI — reflected a deliberate strategic choice: Europe could not compete with TSMC on leading-edge digital logic, but could hold defensible positions in specialized, high-value-added niche technologies where geography and ecosystem depth matter.
French Participants in IPCEI ME I
STMicroelectronics (Geneva HQ, Crolles principal R&D and manufacturing site): ST’s IPCEI ME I role centered on FD-SOI (Fully Depleted Silicon-on-Insulator) commercialization — specifically scaling the 28nm and 22nm FD-SOI nodes from R&D to production volumes for automotive, IoT, and mobile connectivity applications. FD-SOI is not a cutting-edge technology by process node standards (TSMC produces at 3nm; 28nm FD-SOI is “mature” by mainstream metrics). But its power efficiency advantage — a 28nm FD-SOI chip performs equivalently to a 14nm FinFET chip at significantly lower power consumption — makes it the architecture of choice for battery-powered and energy-constrained applications that dominate volume growth in connected devices.
CEA-Leti (Grenoble): The public research laboratory that invented FD-SOI in the 1990s and holds over 3,000 semiconductor patents. CEA-Leti’s IPCEI ME I work covered next-generation FD-SOI nodes (18nm and below), 3D chip stacking (CoolCube — CEA-Leti’s proprietary sequential 3D integration technology), and advanced packaging concepts. CEA-Leti occupies a unique position: it operates as both a national research institution and a commercial technology licensor, with ST, GlobalFoundries, and hundreds of startup clients paying for access to its process development infrastructure.
Soitec (Bernin, Isère, Euronext-listed): The world’s sole commercial manufacturer of SOI wafers, including FD-SOI substrates. Soitec’s IPCEI ME I participation funded capacity expansion and development of its Smart Cut technology for next-generation wafer specifications. The strategic significance of Soitec in the European semiconductor ecosystem is impossible to overstate: there is no FD-SOI manufacturing anywhere on Earth without Soitec. Every FD-SOI chip made by STMicroelectronics in Crolles, by GlobalFoundries in Dresden or Crolles, or by Samsung in Korea starts with a Soitec-manufactured SOI wafer. This is an absolute supply chain monopoly — the kind of chokepoint that US export controls exploit and that Europe’s adversaries would target first in a conflict scenario.
Air Liquide Electronics (specialty gases division): Ultra-pure specialty gases are the hidden critical input of semiconductor manufacturing — nitrogen trifluoride for chamber cleaning, silane for deposition, complex fluorinated compounds for etching. Air Liquide’s IPCEI ME I participation covered advanced specialty gas formulations for FD-SOI processes and on-site gas production at Crolles.
IPCEI ME II: June 2023 — The Scale-Up Program
IPCEI Microelectronics and Communication Technologies II (IPCEI ME/CT II) was approved June 8, 2023 — significantly larger and broader than its predecessor.
Structure:
- 14 EU member states
- €8.1 billion total public funding
- €13.7 billion private investment catalyzed
- 56 direct participants
- 300+ indirect participants and sub-contractors
- Value chain expansion: adds embedded software, semiconductor testing, and communications technologies to ME I’s scope
The STMicroelectronics-GlobalFoundries Crolles Expansion
The centerpiece of France’s IPCEI ME II participation is also France 2030’s largest single industrial investment: the joint STMicroelectronics-GlobalFoundries 300mm fab expansion at Crolles. The project parameters:
Investment: €7.5 billion total (€4.7B private equity and debt, €2.9B France 2030 national grants, €1.5B EU Chips Act) New capacity: 620,000 wafers per year from the new building, alongside Crolles’ existing 500,000 wafers per year from existing facilities Technology: Enhanced FD-SOI at 18nm and below, targeting automotive ADAS chips, industrial IoT, 5G/6G connectivity modules, and low-power AI inference chips Construction: Groundbreaking Q2 2024, first wafers targeted 2027 Employment: 1,000 new ST jobs, 800 new GlobalFoundries jobs, plus 2,000+ supply chain positions
The co-investment structure is critical: GlobalFoundries brings additional production capacity and a global customer base (including AMD for mature node chips); STMicroelectronics brings the FD-SOI technology knowledge and existing customer relationships; France 2030 provides the public capital that makes the economics viable at European labor and energy cost levels.
Soitec Bernin III Expansion
The Crolles expansion creates additional demand for FD-SOI wafers — which only Soitec can produce. Soitec’s IPCEI ME II participation funds construction of Bernin III, the company’s third manufacturing building:
- Investment: €1.2 billion (Soitec equity + France 2030 IPCEI + EU Chips Act)
- Technology: Smart Cut 300mm SOI wafer capacity expansion, plus next-generation substrate types (strained SOI for enhanced carrier mobility, RF-SOI for 5G/6G antenna integrated circuits)
- Construction: 2023-2026
- Impact: Doubles global FD-SOI wafer supply capacity
Bernin III also enables Soitec’s pivot into new substrate markets — germanium-on-insulator for infrared sensing (space and defense applications), gallium nitride on silicon for power electronics, and silicon carbide substrates for EV power modules.
Nano 2030: The French Semiconductor Research Backbone
Concurrent with IPCEI ME II, France 2030 funds the Nano 2030 research program — a €4 billion, 5-year initiative (2022-2027) covering fundamental semiconductor research at CEA-Leti and the Grenoble ecosystem. Nano 2030 has 160+ industrial partners and feeds directly into IPCEI ME II’s innovation requirements, ensuring the basic research pipeline that IPCEI funds cannot cover remains active.
The EU Chips Act Relationship
The EU Chips Act (adopted August 2023, €43 billion total public and private) is architecturally distinct from IPCEI Microelectronics but financially complementary:
| Instrument | Focus | France’s Share |
|---|---|---|
| IPCEI ME I | R&D, compound semiconductors, FD-SOI scale-up | ~€200M |
| IPCEI ME II | FD-SOI gigafactory expansion, advanced packaging | ~€1.6B |
| EU Chips Act Pillar 1 | Leading-edge first-in-kind fabs (2nm target) | €1.5B (Crolles) |
| EU Chips Act Pillar 2 | Existing technology scale-up, supply security | TBD |
| France 2030 national | Nano 2030 research + above | ~€2.9B |
The Chips Act €1.5B confirmed for Crolles in 2024 represents the EU’s direct co-investment in France’s FD-SOI expansion — acknowledging that Crolles is the only location in Europe capable of producing FD-SOI chips at scale.
France’s Semiconductor Moat: A Strategic Assessment
The Crolles-Bernin ecosystem represents Europe’s most defensible semiconductor position precisely because it cannot be replicated:
Geographic lock-in: Soitec wafers are manufactured in Bernin (15 minutes from Crolles). The SOI wafer is a specialty substrate that cannot be produced in a generic fab — it requires Soitec’s proprietary Smart Cut process, 30+ years of refinement, and a specialized workforce. Shipping SOI wafers from France to a theoretical competing FD-SOI fab in Asia would add supply chain fragility and cost.
Ecosystem depth: Within a 100km radius of Crolles: CEA-Leti (R&D), Soitec (wafers), Air Liquide (specialty gases), Applied Materials and Lam Research (equipment service centers), Grenoble INP and UGA (talent pipeline of 1,500+ semiconductor engineers annually). This ecosystem took 40 years to assemble.
Technology moat: FD-SOI’s power efficiency advantage in the connected device market is structural, not cyclical. As battery life and energy efficiency become more important (EVs, IoT, edge AI), FD-SOI’s market expands. The only competing architecture (FinFET/Gate-All-Around) is more expensive to manufacture and consumes more power at equivalent logic performance.
2026 Status
- Crolles expansion: Under construction, on schedule. First wafers from new capacity targeted 2027.
- Soitec Bernin III: ~60% construction complete, on track.
- IPCEI ME III: Commission preliminary discussions ongoing, likely focusing on advanced packaging (chiplet integration), AI accelerator chips, and photonic integrated circuits.
- European semiconductor market share: On track for 11-12% of global output by 2030 (EU 20% target increasingly recognized as aspirational; 15% more realistic).